SOI (silicon on insulator) technology is employed to achieve semiconductor elements with higher speeds and higher degrees of integration. SOI technology includes the steps of forming a semiconductor layer on an insulation board, and then forming semiconductor elements in the semiconductor layer.
For example, U.S. Pat. No. 6,429,486 discloses a semiconductor device employing a semiconductor board with an SOI structure having a buried insulation film.
FIG. 12 is a cross section of the semiconductor device 80 disclosed in U.S. Pat. No. 6,429,486.
The semiconductor device 80 shown in FIG. 12 has a semiconductor substrate 81, an insulation oxide film 82, an SOI layer 83, and an insulation layer oxide film 86. An opening 84 is formed through the insulation oxide film 82 and SOI layer 83, and reaches the semiconductor substrate 81. The opening 84 is filled with a p-type poly-silicon to form a conductor layer 85. An opening 87 is formed through the insulation layer oxide film 86 on the SOI layer 83 and filled with an electrode 88 to form an electrical connection to the conductor layer 85. The electrode 88 formed on the front side of the semiconductor device 80 fixes the potential of the semiconductor substrate 81. For this reason, a semiconductor device is achieved that can prevent malfunctioning of semiconductor elements by fixing the potential of the semiconductor substrate 81, even in a package in which the electrode on its backside cannot be connected to an outside terminal.
Here, flip-chip packaging is employed as a packaging method for highly integrated high-speed semiconductor chips. Flip-chip packaging includes the steps of forming solder bumps on the main side of a semiconductor chip on which semiconductor elements are formed, and then connecting the main side of the chip to a wiring board, on which the chip is to be mounted, via the bumps. Flip-chip packaging is suitable to the high speeds and high degrees of integration of semiconductor chips due to SOI technology because it can lower the wiring delay and downsize the package. In recent years, for flip-chip packaging implementation, CSP (chip size package) structure has been studied, in which the size of the wiring board is made to be nearly the same as the semiconductor chip with the aim of further downsizing.
Semiconductor elements boasting high speeds and high degrees of integration due to SOI technology have had the problem that heat generated during operation cannot be easily radiated outside the semiconductor device due to the presence of substrates having a low thermal conductivity. Even in flip-chip packaging, the heat radiation capability is lower compared to the conventional packaging method of bonding the back side of semiconductor chips to wiring boards, being especially prominent in CSP structures. For this reason, in the highly integrated high-speed semiconductor devices, such problems easily arise as changes in the element characteristics, increase in wiring resistance, melting of the solder bumps, or peeling of the protective film due to thermal stress.
Further, malfunctioning or the like due to noise cannot be completely eliminated, in the semiconductor device 80 shown in FIG. 12, although the potential of the semiconductor substrate 81 is fixed. Therefore, in order to inhibit malfunctioning or the like due to noise, it is necessary to add capacitors, resistors, etc. to a wiring board to form a noise removing circuit. However, mounting these elements inevitably enlarges the overall size of the package.